1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to semiconductor memory devices.
2. Discussion of Related Art
In general, a semiconductor memory device includes a column decoder that decodes a column address signal and outputs a column decoding signal in order to read data stored in a part of a plurality of memory cells connector to an activated word line.
FIG. 1 is a schematic block diagram of s semiconductor memory device in the related art. FIG. 1 shows an example of an X16 Dynamic Random Access Memory (DRAM), which has 16 data I/O pins and can process 16 data. Referring to FIG. 1, a semiconductor memory device 10 includes a memory cell array 11, a column decoder 12, main sense amplifiers 13 to 16, an I/O circuit 17 and 10 pads P1 to P16.
The memory cell array 11 has column memory cell blocks B1 to B4. The semiconductor memory device 10 includes an 8K (8×1024) number of memory cells in a column direction. In other words, one word line (e.g., WL1) is connected to an 8K number of memory cells. Each of the column memory cell blocks B1 to B4 has a 2K (2×1024) number of memory cells in a column direction. The construction of the column memory cell blocks B1 to B4 will be described in more detail below. The construction of the column memory cell blocks B1 to B4 is the same. Therefore, only the column memory cell block B1 will be described as an example. Reference will be made to an exaggerated portion of the column memory cell block B1 in FIG. 1. The column memory cell block B1 includes a plurality of memory cell mats MAT disposed in matrix form. Local I/O lines LIO0 to LIO3 parallel to word lines WL1 to WLn are disposed in twos between the memory cell mats MAT. Furthermore, local I/O lines LIO0, LIO2 parallel to the word lines WL1 to WLn are also disposed at both sides of the outmost of the memory cell mats. Furthermore, the local I/O lines LIO0 to LIO3 are respectively connected to main local I/O lines ML0 to ML3s.
The column decoder 12 decodes a column address signal (ADD_COL). The construction and operation of the column decoder 12 will be described in more detail with reference to FIG. 2. The column decoder 12 includes an address driver 21 and address decoders 22 to 25. The address driver 21 buffer a 9-bit column address signal (ADD_COL) and outputs the result to the address decoders 22 to 25. The address decoder 22 decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_A1 to DEC_A512). The address decoder 23 decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_B1 to DEC_B512). The address decoder 24 decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_C1 to DEC_C512). The address decoder 25 decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_D1 to DEC_D512).
A read operation of the semiconductor memory device 10 will now be described in short. One of (e.g., WL1) of the word lines WL1 to WLn is activated. The column decoder decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_A1 to DEC_A512), DEC_B1 to DEC_B512), DEC_C1 to DEC_C512), DEC_D1 to DEC_D512). The column decoding signals (DEC_A1 to DEC_A512) are input to the mats MAT of the column memory cell block B1, respectively. The column decoding signals (DEC_B1 to DEC_B512) are input to the mats MAT the column memory cell block B2, respectively. Furthermore, the column decoding signals (DEC_C1 to DEC_C512) are input to the mats MAT of the column memory cell block B3, respectively. The column decoding signals (DEC_D1 to DEC_D512) are input to the mats MAT of the column memory cell block B4, respectively. Some data (not shown) of the memory cells included in the mats MAT of the column memory cell block B, are loaded onto the local I/O lines LIO0 to LIO3 in response to the column decoding signals (DEC_A1 to DEC_A512). Thereafter, the data loaded onto the local I/O lines LIO0 to LIO3 are input to the main sense amplifier 13 through the main local I/O lines ML0 to ML3. In the same manner as the column memory cell block B1, data from the column memory cell blocks B2 to B4 are input to the main sense amplifiers 14 to 16 through the main local I/O lines ML4 to ML15.
The main sense amplifier 13 amplifies the data received through the main local I/O lines ML0 to ML3 and outputs the amplified data (ND0 to ND3) to global I/O lines GIO0 to GIO3. The main sense amplifiers 14 to 16 amplify data received through the main local I/O lines ML4 to ML15 and output the amplified data (ND4 to ND15) to global I/O lines GIO4 to GIO15, in the same manner as the main sense amplifier 13.
The I/O circuit 17 outputs the amplified data (ND0 to ND15), which are received through the global I/O lines GIO0 to GIO15, to the output data (DO to D1) through the IO pads P0 to P15. However, if a logic value of any one of 8 bits of the column address signal (ADD_COL) is changed in the semiconductor memory device 10, the address decoders 22 to 25 of the column decoder 12 are all operated. If the address decoders 22 to 25 are operated, a problem arises because high switching current is consumed unnecessarily.
Meanwhile, in the semiconductor memory device 10, the local I/O lines LIO0 to LIO3 included in one column memory cell block must be disposed corresponding to a 2K number of memory cells. Therefore the length (A1) of each of the local I/O lines LIO0 to LIO3 is relatively long. If the length of the local I/O line is long as described above, a voltage of data signals transferred through local I/O lines is attenuated. A problem arises because data cannot be read accurately.